The present disclosure relates to semiconductor devices, and more particularly to layouts of gate patterns.
In general, in processes for fabricating semiconductor devices, a photolithography step including application of a resist, light exposure, and development, an etching step of patterning elements using a resist mask, and a step of removing the resist are repeated to form an integrated circuit on a semiconductor substrate. In recent years, with increasing miniaturization of semiconductor devices, pattern dimensions have been smaller than a wavelength of the exposure light in the photolithography step. Therefore, due to an optical proximity effect of diffracted light, differences between the designed layout dimensions and the pattern dimensions formed on the semiconductor substrate become disadvantageously large.
In order to reduce an optical proximity effect, conventional techniques have designed layouts, for example, a layout in which gate lengths and gate spaces are limited to one or several optional values. The layouts can maintain the finished measurements of the gate lengths to be constant, resulting in reducing variations of the gate lengths due to an optical proximity effect (see Japanese Patent Publication 2007-12855).
Also, Japanese Patent Publication 2008-235350 (FIGS. 1 and 18) shows designing a layout, such as, a layout which maintains not only a regularity of shapes of gate patterns aligned in the horizontal direction of a target gate, but also a regularity of shapes of gate patterns aligned in the vertical direction of the target gate.